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| MAX 3000A (R) Programmable Logic Device Family Data Sheet September 2000, ver. 1.1 Features... s s s s s s s s s s s s s High-performance, low-cost CMOS EEPROM-based programmable logic devices (PLDs) built on a Multiple Array MatriX (MAX(R)) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 Enhanced ISP features: - Enhanced ISP algorithm for faster programming - ISP_Done bit to ensure complete programming - Pull-up resistor on I/O pins during in-system programming High-density PLDs ranging from 600 to 5,000 usable gates 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels Pin counts ranging from 44 to 208 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and plastic J-lead chip carrier (PLCC) packages Hot-socketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance PCI compatible Bus-friendly architecture including programmable slew-rate control Open-drain output option Table 1. MAX 3000A Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tCO1 (ns) fCNT (MHz) Altera Corporation A-DS-M3000A-01.1 EPM3032A 600 32 2 34 4.5 2.9 3.0 227.3 EPM3064A 1,250 64 4 66 4.5 2.8 3.1 222.2 EPM3128A 2,500 128 8 96 5.0 3.3 3.4 192.3 EPM3256A 5,000 256 16 158 5.5 3.9 3.5 172.4 1 MAX 3000A Programmable Logic Device Family Data Sheet ...and More Features s s s s s s s s Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a power reduction of over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs Enhanced architectural features, including: - 6 pin- or logic-driven output enable signals - Two global clock signals with optional inversion - Enhanced interconnect resources for improved routability - Programmable output slew-rate control Software design support and automatic place-and-route provided by the Altera(R) MAX+PLUS(R) II development system for Windows-based PCs and Sun SPARCstations, HP 9000 Series 700/800, and IBM RISC System/6000 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third-party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third-party manufacturers and any in-circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) General Description MAX 3000A devices are low-cost, high-performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. 2 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 2. MAX 3000A Speed Grades Device -4 EPM3032A EPM3064A EPM3128A EPM3256A Note: (1) Contact Altera for up-to-date information on the availability of this speed grade. Speed Grade -5 -6 -7 v v v v (1) v v -10 v v v v v v The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH, and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table 3. Table 3. MAX 3000A Maximum User I/O Pins Device EPM3032A EPM3064A EPM3128A EPM3256A Notes: (1) (2) Contact Altera for up-to-date information on available device package options. When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O pins become JTAG pins. Notes (1), (2) 144-Pin TQFP 208-Pin PQFP 44-Pin PLCC 34 34 44-Pin TQFP 34 34 100-Pin TQFP 66 80 96 116 158 MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. Altera Corporation 3 MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A devices contain 32 to 256 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. MAX 3000A devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixed-voltage systems. MAX 3000A devices are supported by the MAX+PLUS II development system, an integrated package that offers schematic, text--including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIXworkstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. f Functional Description For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. The MAX 3000A architecture includes the following elements: s s s s s Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array (PIA) I/O control blocks The MAX 3000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 3000A devices. 4 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 1. MAX 3000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables LAB A 36 36 6 Output Enables LAB B 6 to 16 I/O 6 to 16 I/O Control Block Macrocells 1 to 16 16 Macrocells 17 to 32 6 to 16 I/O Control Block 6 to 16 I/O 16 6 6 to 16 6 to 16 6 LAB C PIA Macrocells 33 to 48 16 36 36 LAB D 6 to 16 I/O I/O Control Block 6 to 16 Macrocells 49 to 64 6 to 16 I/O Control Block 6 to 16 I/O 16 6 6 to 16 6 to 16 6 Logic Array Blocks The MAX 3000A device architecture is based on the linking of high-performance LABs. LABs consist of 16-macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: s s 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Macrocells MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product-term select matrix, and programmable register. Figure 2 shows a MAX 3000A macrocell. Altera Corporation 5 MAX 3000A Programmable Logic Device Family Data Sheet Figure 2. MAX 3000A Macrocell LAB Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks 2 Programmable Register Register Bypass to I/O Control Block PRN D/T Q ProductTerm Select Matrix VCC Clock/ Enable Select ENA CLRN Clear Select Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms to PIA Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell's register preset, clock, and clock enable control functions. Two kinds of expander product terms ("expanders") are available to supplement macrocell logic resources: s s Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The MAX+PLUS II development system automatically optimizes product-term allocation according to the logic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the MAX+PLUS II software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. 6 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: s s s Global clock signal mode, which achieves the fastest clock-to-output performance. Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 3000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 3000A architecture also offers both shareable and parallel expander product terms ("expanders") that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tSEXP) is incurred when shareable expanders are used. Figure 3 shows how shareable expanders can feed multiple macrocells. Altera Corporation 7 MAX 3000A Programmable Logic Device Family Data Sheet Figure 3. MAX 3000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals from PIA 16 Shared Expanders Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The MAX+PLUS II Compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the MAX+PLUS II Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 x tPEXP. 8 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. Figure 4. MAX 3000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. from Previous Macrocell Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic 36 Signals from PIA 16 Shared Expanders to Next Macrocell Altera Corporation 9 MAX 3000A Programmable Logic Device Family Data Sheet Programmable Interconnect Array Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Figure 5. MAX 3000A PIA Routing to LAB PIA Signals While the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (FPGAs) are cumulative, variable, and path-dependent, the MAX 3000A PIA has a predictable delay. The PIA makes a design's timing performance easy to predict. I/O Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 6 shows the I/O control block for MAX 3000A devices. The I/O control block has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells. 10 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 6. I/O Control Block of MAX 3000A Devices 6 Global Output Enable Signals PIA OE Select Multiplexer VCC to Other I/O Pins from Macrocell GND Open-Drain Output Slew-Rate Control to PIA When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 3000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. Altera Corporation 11 MAX 3000A Programmable Logic Device Family Data Sheet In-System Programmability (ISP) MAX 3000A devices can be programmed in-system via an industrystandard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system programmability (ISP) offers quick, efficient iterations during design development and debugging cycles. The MAX 3000A architecture internally generates the high programming voltages required to program its EEPROM cells, allowing in-system programming with only a single 3.3-V power supply. During in-system programming, the I/O pins are tristated and weakly pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k. MAX 3000A devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that ensures safe operation when in-system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board (PCB) with standard pick-and-place equipment before they are programmed. MAX 3000A devices can be programmed by downloading the information via in-circuit testers, embedded processors, the MasterBlaster communications cable, the ByteBlasterMV parallel port download cable, and the BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling. MAX 3000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. The Jam STAPL can be used to program MAX 3000A devices with incircuit testers, PCs, or embedded processors. f For more information on using the Jam STAPL language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor). MAX 3000A devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. Programming with External Hardware f 12 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The MAX+PLUS II software can use text- or waveform-format test vectors created with the MAX+PLUS II Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. f IEEE Std. 1149.1 (JTAG) Boundary-Scan Support For more information, see Programming Hardware Manufacturers. MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1-1990. Table 4 describes the JTAG instructions supported by MAX 3000A devices. The pin-out tables starting on page 39 of this data sheet show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Table 4. MAX 3000A JTAG Instructions JTAG Instruction SAMPLE/PRELOAD EXTEST BYPASS Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO These instructions are used when programming MAX 3000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL file, JBC file, or SVF file via an embedded processor or test equipment IDCODE USERCODE ISP Instructions The instruction register length of MAX 3000A devices is 10 bits. The IDCODE and USERCODE register length is 32 bits. Tables 5 and 6 show the boundary-scan register length and device IDCODE information for MAX 3000A devices. Altera Corporation 13 MAX 3000A Programmable Logic Device Family Data Sheet Table 5. MAX 3000A Boundary-Scan Register Length Device EPM3032A EPM3064A EPM3128A EPM3256A Boundary-Scan Register Length 96 192 288 480 Table 6. 32-Bit MAX 3000A Device IDCODE Value Device Version (4 Bits) EPM3032A EPM3064A EPM3128A EPM3256A Notes: (1) (2) Note (1) IDCODE (32 bits) Part Number (16 Bits) 0111 0000 0011 0010 0111 0000 0110 0100 0111 0001 0010 1000 0111 0010 0101 0110 Manufacturer's 1 (1 Bit) Identity (11 Bits) (2) 00001101110 00001101110 00001101110 00001101110 1 1 1 1 0001 0001 0001 0001 The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST. 14 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 7 shows the timing information for the JTAG signals. Figure 7. MAX 3000A JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ Table 7 shows the JTAG timing parameters and values for MAX 3000A devices. Altera Corporation 15 MAX 3000A Programmable Logic Device Family Data Sheet Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 25 25 25 Parameter Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 ns ns ns ns ns ns ns ns Programmable Speed/Power Control MAX 3000A devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 3000A device for either high-speed or low-power operation. As a result, speedcritical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tACL, tEN, tCPPW and tSEXP parameters. Output Configuration MAX 3000A device outputs can be programmed to meet a variety of system-level requirements. MultiVolt I/O Interface The MAX 3000A device architecture supports the MultiVolt I/O interface feature, which allows MAX 3000A devices to connect to systems with differing supply voltages. MAX 3000A devices in all packages can be set for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). 16 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 3.0 V incur a nominally greater timing delay of tOD2 instead of tOD1. Inputs can always be driven by 2.5-V, 3.3-V, or 5.0-V signals. Table 8 summarizes the MAX 3000A MultiVolt I/O support. Table 8. MAX 3000A MultiVolt I/O Support VCCIO Voltage 2.5 2.5 3.3 Note: (1) When VCCIO is 3.3 V, a MAX 3000A device can drive a 2.5-V device that has 3.3-V tolerant inputs. Input Signal (V) 3.3 v v 5.0 v v v v Output Signal (V) 2.5 v v (1) 3.3 v 5.0 v Open-Drain Output Option MAX 3000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. Slew-Rate Control The output buffer for each MAX 3000A I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal. Altera Corporation 17 MAX 3000A Programmable Logic Device Family Data Sheet Design Security All MAX 3000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. MAX 3000A devices are fully functionally tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 8. Test patterns can be used and then erased during early stages of the production flow. Figure 8. MAX 3000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V outputs. Numbers without brackets are for 3.3-V devices or outputs. VCC 703 [521 ] Device Output Generic Testing to Test System 620 [481 ] Device input rise and fall times < 2 ns C1 (includes JIG capacitance) Operating Conditions Tables 9 through 12 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for MAX 3000A devices. Note (1) Min -0.5 -2.0 -25 No bias Under bias PQFP and TQFP packages, under bias -65 -65 Table 9. MAX 3000A Device Absolute Maximum Ratings Symbol VCC VI IOUT TSTG TA TJ Parameter Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature Conditions With respect to ground (2) Max 4.6 5.75 25 150 135 135 Unit V V mA C C C 18 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 10. MAX 3000A Device Recommended Operating Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers, 3.3-V operation Supply voltage for output drivers, 2.5-V operation Conditions Min 3.0 3.0 2.3 3.0 Max 3.6 3.6 2.7 3.6 5.75 VCCIO 70 85 90 105 40 40 Unit V V V V V V C C C C ns ns VCCISP VI VO TA TJ tR tF Supply voltage during ISP Input voltage Output voltage Ambient temperature Junction temperature Input rise time Input fall time For commercial use For industrial use For commercial use For industrial use (3) -0.5 0 0 -40 0 -40 Table 11. MAX 3000A Device DC Operating Conditions Symbol VIH VIL VOH Note (4) Min 1.7 -0.5 2.4 VCCIO - 0.2 2.1 2.0 1.7 0.4 0.2 0.2 0.4 0.7 -10 -10 20 10 10 74 Parameter High-level input voltage Low-level input voltage Conditions Max 5.75 0.8 Unit V V V V V V V V V V V V A A k 3.3-V high-level TTL output voltage IOH = -8 mA DC, VCCIO = 3.00 V (5) 3.3-V high-level CMOS output voltage 2.5-V high-level output voltage IOH = -0.1 mA DC, VCCIO = 3.00 V (5) IOH = -100 A DC, VCCIO = 2.30 V (5) IOH = -1 mA DC, VCCIO = 2.30 V (5) IOH = -2 mA DC, VCCIO = 2.30 V (5) VOL 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage 2.5-V low-level output voltage IOL = 8 mA DC, VCCIO = 3.00 V (6) IOL = 0.1 mA DC, VCCIO = 3.00 V (6) IOL = 100 A DC, VCCIO = 2.30 V (6) IOL = 1 mA DC, VCCIO = 2.30 V (6) IOL = 2 mA DC, VCCIO = 2.30 V (6) II IOZ RI S P Input leakage current Tri-state output off-state current Value of I/O pin pull-up resistor when programming in-system or during power-up VI = VCCINT or ground VO = VCCINT or ground VC C I O = 2.3 to 3.6 V (7) Altera Corporation 19 MAX 3000A Programmable Logic Device Family Data Sheet Table 12. MAX 3000A Device Capacitance Symbol CIN CI/O Note (8) Conditions Min Max 8 8 Parameter Input pin capacitance I/O pin capacitance Unit pF pF VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input voltage is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are powered. These values are specified under the recommended operating conditions, as shown in Table 10 on page 19. The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL or CMOS output current. This pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. Capacitance is measured at 25 C and is sample-tested only. The OE1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pF. Figure 9 shows the typical output drive characteristics of MAX 3000A devices. 20 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 9. Output Drive Characteristics of MAX 3000A Devices 3.3 V 150 IOL 100 Typical IO Output Current (mA) 50 VCCINT = 3.3 V VCCIO = 3.3 V O Temperature = 25 C IOH 0 0 1 2 3 4 VO Output Voltage (V) 2.5 V 150 IOL Typical IO Output Current (mA) 100 VCCINT = 3.3 V VCCIO = 2.5 V O Temperature = 25 C 50 IOH 0 0 1 2 3 4 VO Output Voltage (V) Power Sequencing & Hot-Socketing Because MAX 3000A devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The VCCIO and VCCINT power planes can be powered in any order. Signals can be driven into MAX 3000A devices before and during power-up without damaging the device. In addition, MAX 3000A devices do not drive out during power-up. Once operating conditions are reached, MAX 3000A devices operate as specified by the user. Altera Corporation 21 MAX 3000A Programmable Logic Device Family Data Sheet Timing Model MAX 3000A device timing can be analyzed with the MAX+PLUS II software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 10. MAX 3000A devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. Figure 10. MAX 3000A Timing Model Internal Output Enable Delay t IOE Input Delay t IN PIA Delay t PIA Global Control Delay t GLOB Logic Array Delay t LAD Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP Parallel Expander Delay t PEXP Register Delay t SU tH t PRE t CLR t RD t COMB Output Delay t OD1 t OD2 t OD3 t XZ t Z X1 t Z X2 t Z X3 I/O Delay tI O The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 11 shows the timing relationship between internal and external delay parameters. 22 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 11. MAX 3000A Switching Waveforms tR & tF < 2 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Combinatorial Mode tIN Input Pin tIO I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin Global Clock Mode Global Clock Pin Global Clock at Register tR tIN tCH tGLOB tH tCL tF tSU Data or Enable (Logic Array Output) Array Clock Mode tR Input or I/O Pin tACH tIN tIO tACL tF Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array tPIA tIC tSU tH tRD Register to PIA to Logic Array tPIA tOD tCLR , tPRE tOD tPIA Register Output to Pin Altera Corporation 23 MAX 3000A Programmable Logic Device Family Data Sheet Tables 13 through 20 show EPM3032AE, EPM3064A, EPM3128A, and EPM3256A timing information. Table 13. EPM3032A External Timing Parameters Symbol Parameter Conditions -4 Min tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time C1 = 35 pF (2) C1 = 35 pF (2) (2) 2.9 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 (3) 2.0 4.4 227.3 4.4 227.3 138.9 138.9 7.2 103.1 4.3 (2) C1 = 35 pF (2) 3.0 Note (1) Speed Grade -7 Max 4.5 4.5 4.7 0.0 1.0 3.0 3.0 2.5 0.5 1.0 3.0 3.0 3.0 7.2 103.1 9.7 7.2 5.0 Unit -10 Min Max 7.5 7.5 Min Max 10 10 ns ns ns ns 6.7 ns ns ns ns ns 9.4 ns ns ns ns 9.7 ns MHz ns MHz 6.3 0.0 1.0 4.0 4.0 3.6 0.5 1.0 4.0 4.0 4.0 Global clock hold time (2) Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) Maximum internal (2), (4) array clock frequency 24 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 14. EPM3032A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -4 Min tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 Max 0.7 0.7 1.9 0.5 1.5 0.6 0.0 0.8 Unit -10 Min Max 1.2 1.2 3.1 0.8 2.5 1.0 0.0 1.3 Min Max 1.5 1.5 4.0 1.0 3.3 1.2 0.0 1.8 ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF 1.3 1.8 2.3 ns tOD3 C1 = 35 pF 5.8 6.3 6.8 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time 1.3 0.6 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR 4.0 2.0 1.0 0.7 0.6 1.2 0.6 0.8 1.2 1.2 4.0 2.8 1.3 1.2 1.0 2.0 1.0 1.3 1.9 1.9 5.0 ns ns ns 1.5 1.3 2.5 1.2 1.9 2.6 2.6 ns ns ns ns ns ns ns Altera Corporation 25 MAX 3000A Programmable Logic Device Family Data Sheet Table 14. EPM3032A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -4 Min tPIA tLPA PIA delay Low-power adder (2) (5) Note (1) Speed Grade -7 Max 0.9 2.5 Unit -10 Min Max 1.5 4.0 Min Max 2.1 5.0 ns ns 26 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 15. EPM3064A External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -4 -7 Max 4.5 4.5 Unit -10 Min tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time C1 = 35 pF (2) C1 = 35 pF (2) (2) 2.8 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 (3) 2.0 (2) C1 = 35 pF (2) Min Max 7.5 7.5 Min Max 10.0 10.0 ns ns ns ns 7.0 ns ns ns ns ns 9.6 ns ns ns ns 10.0 ns MHz 10.0 ns MHz 4.7 0.0 3.1 1.0 3.0 3.0 2.6 0.4 4.3 1.0 3.0 3.0 3.0 4.5 7.4 135.1 4.5 7.4 135.1 7.2 5.1 6.2 0.0 1.0 4.0 4.0 3.6 0.6 1.0 4.0 4.0 4.0 Global clock hold time (2) Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 222.2 222.2 100.0 Maximum internal (2), (4) array clock frequency 100.0 Altera Corporation 27 MAX 3000A Programmable Logic Device Family Data Sheet Table 16. EPM3064A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -4 Min tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 Max 0.6 0.6 1.8 0.4 1.5 0.6 0.0 0.8 Unit -10 Min Max 1.1 1.1 3.0 0.7 2.5 1.0 0.0 1.3 Min Max 1.4 1.4 3.9 0.9 3.2 1.2 0.0 1.8 ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF 1.3 1.8 2.3 ns tOD3 C1 = 35 pF 5.8 6.3 6.8 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time 1.3 0.6 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR 4.0 2.0 1.0 0.7 0.6 1.2 0.6 1.0 1.3 1.3 4.0 2.9 1.3 1.2 0.9 1.9 1.0 1.5 2.1 2.1 5.0 ns ns ns 1.6 1.3 2.5 1.2 2.2 2.9 2.9 ns ns ns ns ns ns ns 28 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 16. EPM3064A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -4 Min tPIA tLPA PIA delay Low-power adder (2) (5) Note (1) Speed Grade -7 Max 1.0 3.5 Unit -10 Min Max 1.7 4.0 Min Max 2.3 5.0 ns ns Altera Corporation 29 MAX 3000A Programmable Logic Device Family Data Sheet Table 17. EPM3128A External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 -7 Max 5.0 5.0 Unit -10 Min tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time C1 = 35 pF (2) C1 = 35 pF (2) (2) 3.3 0.0 1.0 2.0 2.0 1.8 0.2 1.0 2.0 2.0 (3) 2.0 (2) C1 = 35 pF (2) Min Max 7.5 7.5 Min Max 10 10 ns ns ns ns 6.6 ns ns ns ns ns 9.4 ns ns ns ns 10.2 ns MHz 10.2 ns MHz 4.9 0.0 3.4 1.0 3.0 3.0 2.8 0.3 4.9 1.0 3.0 3.0 3.0 5.2 7.7 129.9 5.2 7.7 129.9 7.1 5.0 6.6 0.0 1.0 4.0 4.0 3.8 0.4 1.0 4.0 4.0 4.0 Global clock hold time (2) Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 192.3 192.3 98.0 Maximum internal (2), (4) array clock frequency 98.0 30 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 18. EPM3128A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Min tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 Max 0.7 0.7 2.0 0.4 1.6 0.7 0.0 0.8 Unit -10 Min Max 1.0 1.0 2.9 0.7 2.4 1.0 0.0 1.2 Min Max 1.4 1.4 3.8 0.9 3.1 1.3 0.0 1.6 ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF 1.3 1.7 2.1 ns tOD3 C1 = 35 pF 5.8 6.2 6.6 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time 1.4 0.6 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR 4.0 2.1 1.0 0.8 0.5 1.2 0.7 1.1 1.4 1.4 4.0 2.9 1.3 1.2 0.9 1.7 1.0 1.6 2.0 2.0 5.0 ns ns ns 1.6 1.3 2.2 1.3 2.0 2.7 2.7 ns ns ns ns ns ns ns Altera Corporation 31 MAX 3000A Programmable Logic Device Family Data Sheet Table 18. EPM3128A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min tPIA tLPA PIA delay Low-power adder (2) (5) Note (1) Speed Grade -7 Max 1.4 4.0 Unit -10 Min Max 2.0 4.0 Min Max 2.6 5.0 ns ns 32 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 19. EPM3256A External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 -7 Max 5.5 5.5 Unit -10 Min tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time C1 = 35 pF (2) C1 = 35 pF (2) (2) 3.9 0.0 1.0 2.0 2.0 2.0 0.2 1.0 2.0 2.0 (3) 2.0 (2) C1 = 35 pF (2) Min Max 7.5 7.5 Min Max 10 10 ns ns ns ns 6.4 ns ns ns ns ns 9.7 ns ns ns ns 10.5 ns MHz 10.5 ns MHz 5.2 0.0 3.5 1.0 3.0 3.0 2.7 0.3 5.4 1.0 3.0 3.0 3.0 5.8 7.9 126.6 5.8 7.9 126.6 7.3 4.8 6.9 0.0 1.0 4.0 4.0 3.6 0.5 1.0 4.0 4.0 4.0 Global clock hold time (2) Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 172.4 172.4 95.2 Maximum internal (2), (4) array clock frequency 95.2 Altera Corporation 33 MAX 3000A Programmable Logic Device Family Data Sheet Table 20. EPM3256A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Min tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 Max 0.7 0.7 2.1 0.3 1.7 0.8 0.0 0.9 Unit -10 Min Max 0.9 0.9 2.8 0.5 2.2 1.0 0.0 1.2 Min Max 1.2 1.2 3.7 0.6 2.8 1.3 0.0 1.6 ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF 1.4 1.7 2.1 ns tOD3 C1 = 35 pF 5.9 6.2 6.6 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time 1.5 0.7 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR 4.0 2.1 0.9 0.9 0.5 1.2 0.8 1.0 1.6 1.6 4.0 2.9 1.2 1.2 0.8 1.6 1.0 1.5 2.3 2.3 5.0 ns ns ns 1.6 1.2 2.1 1.3 2.0 3.0 3.0 ns ns ns ns ns ns ns 34 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 20. EPM3256A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min tPIA tLPA PIA delay Low-power adder (2) (5) Note (1) Speed Grade -7 Max 1.7 4.0 Unit -10 Min Max 2.4 4.0 Min Max 3.2 5.0 ns ns Notes to tables: (1) (2) (3) These values are specified in Tables 13 through 20 under the recommended operating conditions shown in Table 9 on page 18. These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in low-power mode. (4) (5) Power Consumption Supply power (P) versus frequency (fMAX, in MHz) for MAX 3000A devices is calculated with the following equation: P = PINT + PIO = ICCINT x VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation: ICCINT = (A x MCTON) + [B x (MCDEV - MCTON)] + (C x MCUSED x fMAX x togLC) Altera Corporation 35 MAX 3000A Programmable Logic Device Family Data Sheet The parameters in the ICCINT equation are: MCTON = Number of macrocells with the Turbo BitTM option turned on, as reported in the MAX+PLUS II Report File (.rpt) MCDEV = Number of macrocells in the device MCUSED = Total number of macrocells in the design, as reported in the RPT File fMAX = Highest clock frequency to the device = Average percentage of logic cells toggling at each clock togLC (typically 12.5%) A, B, C = Constants (shown in Table 21) Table 21. MAX 3000A ICC Equation Constants Device EPM3032A EPM3064A EPM3128A EPM3256A A 0.85 0.85 0.85 0.85 B 0.36 0.36 0.36 0.36 C 0.017 0.017 0.017 0.017 The ICCINT calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. 36 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figures 12 and 13 shows the typical supply current versus frequency for MAX 3000A devices. Figure 12. ICC vs. Frequency for MAX 3000A Devices (Part 1 of 2) EPM3032A VCC = 3.3 V Room Temperature 70 60 50 Typical ICC Active (mA) 40 30 20 10 High Speed 227.3 MHz 144.9 MHz Non-Turbo 0 50 100 150 200 250 Frequency (MHz) EPM3064A VCC = 3.3 V Room Temperature 140 120 100 Typical ICC Active (mA) 80 60 40 20 High Speed 222.2 MHz 125.0 MHz Non-Turbo 0 50 100 150 200 250 Frequency (MHz) Altera Corporation 37 MAX 3000A Programmable Logic Device Family Data Sheet Figure 13. ICC vs. Frequency for MAX 3000A Devices (Part 2 of 2) EPM3128A VCC = 3.3 V Room Temperature 210 180 150 High Speed 192.3 MHz Typical ICC Active (mA) 120 90 108.7 MHz 60 30 Non-Turbo 0 50 100 150 200 250 Frequency (MHz) EPM3256A VCC = 3.3 V Room Temperature 350 300 250 172.4 MHz Typical ICC Active (mA) 200 150 100 50 High Speed 102.0 MHz Non-Turbo 0 50 100 150 200 Frequency (MHz) 38 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Device Pin-Outs Tables 22 through 29 show the pin names and numbers for the pins in MAX 3000A device packages. Table 22. EPM3032A Dedicated Pin-Outs Dedicated Pin INPUT/GCLK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2/GCLK2 TDI (1) TMS (1) TCK (1) TDO (1) GNDINT GNDIO VCCINT (3.3 V) VCCIO (2.5 V or 3.3 V) No Connect (N.C.) Total User I/O Pins (2) 43 1 44 2 7 13 32 38 22, 42 10, 17, 30, 36 3, 23 15, 35 - 34 44-Pin PLCC 37 39 38 40 1 7 26 32 44-Pin TQFP 16, 36 4, 11, 24, 30 17, 41 9, 29 - 34 Altera Corporation 39 MAX 3000A Programmable Logic Device Family Data Sheet Table 23. EPM3032A I/O Pin-Outs LAB A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Notes to tables: (1) (2) This pin may function as either a JTAG port or a user I/O pin. When the device is configured to use the JTAG ports for in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all I/O pins. MC 4 5 6 44-Pin PLCC 42 43 44 44-Pin TQFP LAB B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MC 41 40 39 44-Pin PLCC 35 34 33 44-Pin TQFP 7 (1) 8 9 11 12 13 (1) 14 16 - 18 19 20 21 1 (1) 2 3 5 6 7 (1) 8 10 - 12 13 14 15 38 (1) 37 - 34 33 32 (1) 31 29 28 27 26 25 24 32 (1) 31 - 28 27 26 (1) 25 23 22 21 20 19 18 40 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 24. EPM3064A Dedicated Pin-Outs Dedicated Pin INPUT/GCLK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2/GCLK2 TDI (1) TMS (1) TCK (1) TDO (1) GNDINT GNDIO VCCINT (3.3 V Only) 43 1 44 2 7 13 32 38 22, 42 10, 17, 30, 36 3, 23 44-Pin PLCC 37 39 38 40 1 7 26 32 44-Pin TQFP 87 89 88 90 4 15 62 73 100-Pin TQFP 16, 36 4, 11, 24, 30 17, 41 9, 29 - 38, 86 11, 26, 33, 43, 53, 59, 65, 74, 78, 95 39, 91 3, 18, 34, 51, 66, 82 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 55, 70, 72, 77 66 VCCIO (2.5 V or 3.3 V) 15, 35 No Connect (N.C.) - Total User I/O Pins (2) 34 34 Altera Corporation 41 MAX 3000A Programmable Logic Device Family Data Sheet Table 25. EPM3064A I/O Pin-Outs LAB A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes to tables: (1) (2) This pin may function as either a JTAG port or a user I/O pin. When the device is configured to use the JTAG ports for in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all I/O pins. MC 44-Pin PLCC 12 - 11 9 8 - - 7 (1) - - 6 - - 5 - 4 21 - 20 19 18 - - - 16 - - - - 14 - 13 (1) 6 - 5 3 2 - - 44-Pin TQFP 100-Pin TQFP 14 13 12 10 9 8 6 4 (1) 100 99 98 97 96 94 93 92 37 36 35 - 32 31 30 29 25 23 21 20 19 17 16 15 (1) LAB C 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D 49 50 51 52 53 54 55 56 57 48 59 60 61 62 63 64 MC 44-Pin PLCC 24 - 25 26 27 - - 28 29 - - - - 31 - 32 (1) 33 - 34 - 37 - - 38 (1) 39 - - - - 40 - 41 - 44-Pin TQFP 18 19 20 21 - - 22 23 - - - - 25 - 26 (1) 27 - 28 - 31 - - 32 (1) 33 - - - - 34 - 35 100-Pin TQFP 40 41 42 44 45 46 47 48 52 54 56 57 58 60 61 62 (1) 63 64 - 67 68 69 71 73 (1) 75 76 79 80 81 83 84 85 1 (1) - - 44 - - 43 - 42 15 - 14 13 12 - - - 10 - - - - 8 - 7 (1) 42 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 26. EPM3128A Dedicated Pin-Outs Dedicated Pin INPUT/GCLK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2/GCLK2 TDI (1) TMS (1) TCK (1) TDO (1) GNDINT GNDIO VCCINT (3.3 V Only) No Connect (N.C.) 87 89 88 90 4 15 62 73 38, 86 11, 26, 33, 43, 53, 59, 65, 74, 78, 95 39, 91 - 100-Pin TQFP 125 127 126 128 4 20 89 104 144-Pin TQFP 52, 57, 124, 129 3, 13, 17, 26, 33, 59, 64, 77, 85, 94, 105, 114, 135 51, 58, 123, 130 24, 50, 73, 76, 95, 115, 144 1, 2, 12, 19, 34, 35, 36, 43, 46, 47, 48, 49, 66, 75, 90, 103, 108, 120, 121, 122 96 VCCIO (2.5 V or 3.3 V) 3, 18, 34, 51, 66, 82 Total User I/O Pins (2) 80 Altera Corporation 43 MAX 3000A Programmable Logic Device Family Data Sheet Table 27. EPM3128A I/O Pin-Outs (Part 1 of 2) LAB A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MC 2 - 1 - 100-Pin TQFP - 144-Pin TQFP 143 142 141 140 139 - 138 137 - 136 134 133 132 - 131 18 - 16 15 14 11 - 10 9 - 8 7 6 5 - 4 (1) LAB C 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MC 100-Pin TQFP 25 - 24 - 23 22 - 21 20 - 19 - 17 16 - 15 (1) 37 - 36 - 35 - - 32 31 - 30 - 29 28 - 27 - 144-Pin TQFP 32 31 30 29 28 - 27 - - 25 23 22 21 - 20 (1) 56 - 55 54 53 45 - 44 42 - 41 40 39 38 - 37 100 99 - 98 97 - 96 - 94 93 - 92 14 - 13 - 12 10 - 9 8 - 7 - 6 5 - 4 (1) 44 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 27. EPM3128A I/O Pin-Outs (Part 2 of 2) LAB E 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 F 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Notes to tables: (1) (2) This pin may function as either a JTAG port or a user I/O pin. When the device is configured to use the JTAG ports for in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all I/O pins. MC 100-Pin TQFP 40 - 41 - 42 44 - 45 46 - 47 - 48 49 - 50 52 - - - 54 55 - 56 57 - 58 - 60 61 - 62 (1) - 144-Pin TQFP 60 61 62 63 65 - 67 68 - 69 70 71 72 - 74 - - 78 79 80 81 - 82 83 - 84 86 87 88 - 89 (1) LAB G 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 H 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 MC 100-Pin TQFP 63 - 64 - - 67 - 68 69 - 70 - 71 72 - 73 (1) 75 - 76 - 77 - - 79 80 - 81 - 83 84 - 85 - 144-Pin TQFP 91 92 93 - 96 - 97 98 - 99 100 101 102 - 104 (1) 106 - 107 109 110 111 - 112 113 - - 116 117 118 - 119 Altera Corporation 45 MAX 3000A Programmable Logic Device Family Data Sheet Table 28. EPM3256A Dedicated Pin-Outs Dedicated Pin INPUT/GCLK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2/GCLK2 TDI (1) TMS (1) TCK (1) TDO (1) GNDINT GNDIO 125 127 126 128 4 20 89 104 52, 57, 124, 129 144-Pin TQFP 184 182 183 181 176 127 30 189 208-Pin PQFP 75, 82, 180, 185 3, 13, 17, 26, 33, 59, 64, 6, 14, 32, 40, 50, 72, 84, 77, 85, 94, 105, 114, 135 94, 108, 116, 134, 142, 152, 174, 190, 200 51, 58, 123, 130 24, 50, 73, 76, 95, 115, 144 - 74, 83, 179, 186 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 1, 2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 158 VCCINT (3.3 V Only) VCCIO (2.5 V or 3.3 V) No Connect (N.C.) Total User I/O Pins (2) 116 46 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 29. EPM3256A I/O Pin-Outs (Part 1 of 4) LAB A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MC - - 2 - 1 144-Pin TQFP - 208-Pin PQFP 153 154 - 159 160 - 161 162 - 163 - 164 166 - 167 141 - - - 144 145 - 146 147 - 148 - 149 150 - 151 LAB C 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MC 144-Pin TQFP 36 - 35 - 34 - - 32 31 - 30 - 29 - - 28 44 - 43 - 42 41 - 40 - - 39 - 38 - - 37 - - 208-Pin PQFP 109 - 110 111 - 112 113 - 114 - 115 117 - 118 92 - 93 - 95 96 - 97 98 - 99 - 100 101 - 102 143 - - - - 142 - 141 140 - 139 - - 10 - 9 - - 8 7 - 6 - 5 - - 4 (1) Altera Corporation 47 MAX 3000A Programmable Logic Device Family Data Sheet Table 29. EPM3256A I/O Pin-Outs (Part 2 of 4) LAB E 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 F 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 MC - - - - 144-Pin TQFP - 208-Pin PQFP 168 169 - 170 171 - 172 173 - 175 - 176 (1) 177 - 178 130 - 131 - 132 133 - 135 136 - 137 - 138 139 - 140 LAB G 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 H 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 MC - - 144-Pin TQFP - 208-Pin PQFP 119 120 - 121 122 - 123 124 - 126 - 127 (1) 128 - 129 79 - 80 - 81 - - 86 87 - 88 - 89 90 - 91 27 - - - - 25 23 - 22 - 21 - - 20 (1) - - 54 - 53 - - 49 48 - 47 - 46 - - 45 138 - - 137 136 - 134 - 133 132 - 131 - - 19 - 18 - - 16 15 - 14 - 12 - - 11 48 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 29. EPM3256A I/O Pin-Outs (Part 3 of 4) LAB I 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 J 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 MC - - 144-Pin TQFP - 208-Pin PQFP 197 196 - 195 194 - 193 192 - - - 189 (1) 188 - 187 27 - 26 - 25 24 - 22 21 - 20 - 19 18 - 17 LAB K 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 L 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 MC - - 144-Pin TQFP - 208-Pin PQFP 38 37 - 36 35 - 34 33 - 31 - 30 (1) 29 - 28 78 - 77 - 76 73 - 71 70 - 69 - 68 67 - 66 116 - 117 - - 118 119 - 120 - 121 - - 122 - - 90 - 91 - - 92 93 - - - 96 - - 97 82 - 83 - - 84 86 - 87 - 88 - - 89 (1) - - 55 - 56 - - 60 61 - 62 - 63 - - 65 Altera Corporation 49 MAX 3000A Programmable Logic Device Family Data Sheet Table 29. EPM3256A I/O Pin-Outs (Part 4 of 4) LAB M 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 N 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 Notes to tables: (1) (2) This pin can function as either a JTAG pin or a user I/O pin. When the device is programmed to use the JTAG ports for boundary-scan testing or in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all I/O pins. MC 144-Pin TQFP 106 - 107 - 108 - - 109 110 - 111 - - 112 - 113 - - 98 - 99 - - 100 101 - 102 - 103 - - 104 (1) 4 - 3 - 208-Pin PQFP LAB O 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 P 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 MC - - 144-Pin TQFP - 208-Pin PQFP 49 48 - 47 46 - 45 44 - 43 - 42 - - 39 65 - 64 - 62 61 - 60 59 - 58 - 57 56 - 55 74 - 75 - - - 78 - 79 - 80 - - 81 66 - 67 - 68 69 - - 70 - - - 71 - - 72 206 205 - 204 203 - 202 - 201 199 - 198 16 - 15 - 13 12 - 11 10 - 9 - 8 7 - - 50 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figures 14 through 17 show the package pin-out diagrams for MAX 3000A devices. Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram Package outlines not drawn to scale. INPUT/OE2/GCLK2 INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/GCLRn INPUT/GCLK1 INPUT/GCLK1 INPUT/OE1 INPUT/OE1 GND GND VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin 1 39 38 37 36 35 I/O I/O/TDO I/O GND VCC I/O I/O I/O/TCK I/O GND I/O Pin 34 6 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O GND 7 8 9 10 11 12 13 14 15 16 17 54 3 2 1 44 43 42 41 40 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O GND I/O I/O/TDO I/O GND VCC EPM3032A EPM3064A 34 33 32 31 30 29 EPM3032A EPM3064A I/O I/O I/O/TCK I/O GND I/O 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin 12 VCC I/O Pin 23 44-Pin PLCC 44-Pin TQFP Figure 15. 100-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 76 EPM3064A EPM3128A Pin 26 Pin 51 Altera Corporation 51 MAX 3000A Programmable Logic Device Family Data Sheet Figure 16. 144-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Pin 1 Pin 1 Pin 109 EPM3128A EPM3256A Pin 37 Pin 73 Figure 17. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 157 EPM3256A Pin 53 Pin 105 52 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Revision History The information contained in the MAX 3000A Programmable Logic Device Family Data Sheet version 1.1 supersedes information published in previous versions. Version 1.1 Changes MAX 3000A Programmable Logic Device Family Data Sheet version 1.1 contains the following changes: s s s s s s s Made minor style and textual changes Updated timing values in Table 1 and Tables 13 through 20 Updated Table 2 and Note (1) Removed QuartusTM information throughout the document Updated Notes to Table 10 Updated drive characteristics in Figure 9 Updated ICC current constants in Table 21 and Figures 12 and 13 Version 1.01 Changes MAX 3000A Programmable Logic Device Family Data Sheet version 1.01 contains the following changes: s s s s s s s Corrected Figure 2 Corrected notes in Tables 10 and 11 Corrected the maximum VOL value for 3.3-V low-level TTL output voltage in Table 11 Added the tCPPW parameter to Tables 13 and 15 Updated Table 21 Updated Figure 12 Corrected total I/O count for EPM3064A devices in 100-pin TQFP packages in Tables 3 and 24 (R) 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com Altera, BitBlaster, ByteBlasterMV, MasterBlaster, Quartus, EPM3032A, EPM3064A, EPM3128A, EPM3256A, Jam, MAX, MAX 3000A, MAX+PLUS, MAX+PLUS II, Turbo Bit, MultiVolt , and specific device designations are trademarks and/or service marks of Altera Corporation in the United States or other countries. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog is a registered trademark of Cadence Design Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright 2000 Altera Corporation. All rights reserved. 53 Printed on Recycled Paper. Altera Corporation |
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